Microprocessor

High low range voltages

0 and 1 are representation of logic levels, 0 is low while 1 is high. If voltage falls between 0 and +0.8 volts the mode is considered as logic 0. If voltage falls between +2 and +5 volts node is classified as logic 1.

 

Parallel signal transmissions

Each bit derived from separate output signal in parallel signal transmission and transmitted over separate line.

Five circuit outputs are present simultaneously, complete binary number appear at outputs. Binary number presentation is 10110.

 

Serial signal transmissions

Only one signal output is used to transmit the binary number in serial signal transmissions. The output line transmits one bit at a time  LSB (least significant bit). So you will need a timer to distinguish between individual bit. A clock signal do this job. Whenever a clock pulse occurs output signal change to the next bit.

Since LSB transmit first we read the binary number as 11010.

 

Three state logic

A three state logic circuit has three output, besides high and low there is also high impedance or high-z state.

 

Tristate buffer determines

ENABLE input determines the output operation so that the output acts as either normal output (ENABLE=0) or as a high-Z output (ENABLE=1).

 

ENABLE DISABLE condition

In ENABLE condition, circuit behaves exactly as any logic buffer gate, producing an output equivalent to its input. DISABLE means high 2 state output not connected to input consider the node as a virtual open circuit.

 

74HC125

74HC125 is a tristate buffer IC with schematic diagram like below:

Active Low Active High

 E means as active low indicated by the small circle on the device symbol. Buffer is activated when ENABLE is low. 74HC125 is active low but 74HC126 is active high that is buffer is activated when ENABLE is high.

Tri-state Buffer applications

When several logic signals connected to a common line called a bus tri-state buffer will be used. Tri-state buffer application can be arranged like this:

Bus Contention defects

Defects of bus contention is that one output is trying to go to LOW while the other trying to go to HIGH, excessive current resulted in damage to the buffer's output circuitry.

 

Examples tri-state circuits

Flip-flops

Registers

Memories

Microcomputer

Microprocessor

Interface chips

 

Logic Gates Memory

Logic gates memory produce outputs depends on the input of the current logic states. Digital systems require logic circuits that can produce outputs depend on previous state of inputs.

 

Flip-flops conditions

A flip-flop circuit will retain any data in its circuit even after inputs connection is terminated.

 

General flip-flop symbol

 

Operated NAND gates flip-flop truth table

NAND gates flip-flop has the following truth table. Based on this truth table, NAND operation can be understood:

SET	CLEAR	Q
1	1	No change
0	1	1
1	0	0
0	0	Ambiguous

SET and CLEAR start at digital inputs 1 when SET set to 0, Q will goes to 1. When SET set back to 1, Q still remains at 1. At this time the flip-flop is said to be set. When CLEAR set to 0 Q will go to the 0 state and it will stay there. At this time flip-flop is said to be cleared. Remember that never set SET and CLEAR to 0. Another name for CLEAR is RESET input.

 

Master Clock Signal

Master clock signal will generate periodic pulses distributed to all parts of the circuits then synchronized all sequence of operations and we call this digital system as synchronous sequential systems.

 

Clock signals defined

The transition from 0 to 1 is defined the rising edge or positive going edge of the clock signal. The transition from 1 to 0 is defined the falling edge or negative going edge of the clock signal

Clocked flip-flop

Clocked flip-flop change state at appropriate clock transition then rest between successive clock pulses.

 

Frequency clock pulses

Frequency clock pulses depends on how long flip-flops have to respond to the level changes from 1 to m0 or 0 to 1 initiated by clock pulse. This is called the propagation delay of the logic circuits.

 

Clocked flip-flop inputs

Clocked flip-flops inputs are of two types, CLK and control inputs. When you applied signal to CLK the another control inputs determine what state the flip-flop output will become, signal at CLK input is the actual triggering signal that allows flip-flop to respond to the control inputs.

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